1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly to a method for isolating transistors after formation of the transistor devices.
2. Description of the Relevant Art
In a metal-oxide-semiconductor (MOS) integrated circuits, a plurality of transistors are fabricated within and upon a monolithic semiconductor substrate typically comprised of doped silicon. To effectively isolate individual transistors from one another so that the individual devices may be selectively interconnected to achieve a desired function, isolation structures must be included in the integrated circuit. In the absence of adequate isolation structures, an individual transistor could undesirably become electrically coupled to a neighboring transistor. Such undesirable and unpredictable coupling of transistors within a semiconductor can render the device non-functional.
Fabrication of a metal-oxide-semiconductor ("MOS") transistor is well-known. Fabrication begins by lightly doping a single crystal silicon substrate n-type or p-type. A gate dielectric may be formed by oxidizing the silicon substrate. Oxidation is generally performed in a thermal oxidation furnace or, alternatively, in a rapid thermal anneal ("RTA") apparatus. A gate conductor is then patterned from a layer of polycrystalline silicon ("polysilicon") deposited upon the gate dielectric. The polysilicon is rendered conductive by doping it with ions from an implanter or a diffusion furnace. The gate conductor is patterned using a mask followed by exposure, development, and etching. Subsequently, source and drain regions are doped, via ion implantation, with a high dosage n-type or p-type dopant. If the source and drain regions are doped n-type, the transistor is referred to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When voltage above a certain threshold is applied to the gate of an enhancement-mode transistor, the channel between the source and drain becomes conductive and the transistor turns on.
NMOS remained the dominant MOS technology as long as the integration level of devices on a chip was sufficiently low. NMOS is somewhat inexpensive to fabricate, functionally dense, and faster than PMOS. NMOS logic gates (i.e., inverters) draw DC power during one of the inverter states. Therefore, an NMOS integrated circuit will draw a steady current even when being operated in the standby mode (i.e., even when no signal is being propagated through the circuit). During the modern VLSI era, power consumption in NMOS circuits began to exceed tolerable limits. A lower power technology was needed to exploit the VLSI techniques. Complimentary MOS ("CMOS") represented such a technology. CMOS is called so because it uses a combination of an NMOS transistor with a PMOS transistor. Therefore, in a CMOS inverter (unlike in an NMOS inverter) only one of the two transistors is driven at any one time. This means that when a CMOS inverter is not switching from one state to the other, a high impedance path exists from the supply voltage to ground, regardless of the state the inverter is in. Hence, virtually no current flows, and almost no DC power is dissipated. CMOS thus allows the manufacture of circuits with standby power on the order of microwatts.
For a CMOS integrated circuit, both NMOS and PMOS type transistors must be fabricated on the same wafer. On a given substrate which is initially doped n-type or p-type, only one type of transistor can be formed. To accommodate the device type that cannot be built on this substrate, regions of a doping type opposite of that present in the starting material must be formed. The regions of opposite doping, called wells (or sometimes tubs), are the first features to be defined on a starting wafer. This can be accomplished by implanting and then diffusing an appropriate dopant to attain the proper well depth and doping profile. For an initially n-type substrate a p-type dopant such as boron is used to form a p-well, while for an initially p-type substrate an n-type dopant such as phosphorus or arsenic is used to form an n-well.
Historically, the predominant MOS transistor isolation method has been the local oxidation (LOCOS) process. In the LOCOS process, as is well known in the field of semiconductor processing, a relatively thick thermal oxide film is formed between the source drain regions of neighboring transistor devices. The thermally grown oxide film, commonly referred to as the field oxide, consumes silicon within the silicon substrate surface such that the field oxide tends to form partially within and partially upon the silicon substrate. More specifically, approximately 45% of a field oxide film will extend into the silicon substrate while the remaining 55% grows above the silicon substrate upper surface. Field oxide formation is suppressed in regions of the silicon substrate wherein active devices will subsequently be formed by depositing a layer of silicon nitride over the active regions prior to the formation of the field oxide. The silicon nitride is typically deposited on a thin "pad" oxide to relieve the stress that silicon nitride films impart to a silicon surface. The thick field oxide film serves to isolate active regions displaced on either side of the field oxide film. To enhance the isolation capabilities of the field oxide, an implant is commonly performed to introduce impurities into a region under the field oxide. The polarity or conductivity type of the impurity introduced under the field oxide film is opposite the conductivity type of the subsequently formed source/drain regions.
Typical LOCOS field oxide films grow with a characteristic bird's beak structure that extends partially into the active regions of the neighboring transistors. This encroachment upon the transistor active region by the field oxide structure coupled with the portion of the field oxide that forms above the semiconductor substrate surface result in a non-planar surface upon which the transistors must be subsequently formed. As the geometries of semiconductor devices decrease below the sub 0.5 micron range, the planarity of the surface upon which transistors are formed becomes increasingly important. For example, short-channel effects (SCE), which can result in increased subthreshold leakage, can become exaggerated when transistors are formed upon a non-planar surface.
One method of improving the planarity of MOS isolation structures is the shallow trench isolation (STI) process. In an STI process, a trench is etched into the silicon substrate and subsequently filled with a dielectric material, typically an oxide. A planarization step is then performed to remove the oxide from regions exterior to the isolation trench. Ideally, the upper surface of the semiconductor substrate is completely planar after the planarization of the trench dielectric. Although the STI process is theoretically capable of producing a planar surface upon which transistors can be formed, significant processing is required to achieve the planar surface prior to the formation of the transistors. Specifically, it may be necessary to perform a number of chemical-mechanical polish steps, possibly in combination with some selective masking steps and some plasma etch steps to achieve the desired planarity. The incorporation of these processing steps prior to the formation of a gate dielectric is generally undesirable because of the increased potential for generating defects in critical regions of the silicon substrate and because of the high particle counts associated with these planarization processing steps.
In both the LOCOS process and the STI process, the isolation dielectric must be formed with an initial thickness substantially greater than the final desired thickness of the film. The additional film thickness is necessary because of the presence of subsequent processing steps that reduce the isolation dielectric thickness. More specifically, the typical transistor formation process includes cleaning and wafer preparation steps that require immersion in hydrofluoric acid ("HF"). In addition, the incorporation of "spacer" structures into many MOS processes necessitates a spacer etch step. The HF dip process steps and spacer etch process step attack the isolation dielectric and reduce the isolation film thickness. Thus, the original film thickness must be increased to compensate for these film reducing process steps. Since thicker films generally require more processing time, the need to overgrow or "over deposit" the isolation dielectric is an undesirable result. In addition, the numerous post-formation processing steps that attack the isolation dielectric make it more difficult to control the final film thickness. To accommodate the film thickness variations that can result because of the multiple processing steps that etch the isolation dielectric, the process specification must be relaxed. Generally, it is more desirable to have a narrow specified range for any given process parameter to reduce the variability in the operating characteristics of the finished product.
Therefore, it is desirable to implement a semiconductor process in which the gate dielectric and subsequent transistor formation processing steps are performed upon a planar silicon substrate without requiring a significant increase in the pre-transistor formation processing. It is also desirable to reduce or eliminate the number of oxide etch steps to which the isolation dielectric is subjected. It is further desirable to reduce the amount of dopants contaminating the trench dielectric. When the trench is formed early in the process, the trench dielectric is exposed to all subsequent ion implantations and thermal anneals which may introduce dopants into the trench dielectric. Such dopants may change the dielectric constant of the trench dielectric and reduce its insulating capabilities.